`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yu Zihao
// 
// Create Date: 2021/08/14 16:03:59
// Design Name: 
// Module Name: lab7_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lab7_tb();

reg clk,reset;
reg [7:0] SW;
wire [7:0] LEDR;

initial begin
    clk = 0;
    SW = 8'b1000011101;
    reset = 0;
    #2;
    reset = 1;
    #2;
    reset = 0;
    #2;
    repeat(500) #1
    begin
        clk <= ~clk;
    end
    $stop;
end

lab7_top lab7_ins(clk,reset,SW,LEDR);

endmodule
